1. Field of the Invention
The present invention relates to a structure for preventing field concentration caused in an end portion of a semiconductor region, which is formed by p-n junction isolation on a semiconductor substrate, provided under a conductive layer, which extends above the semiconductor region across the end portion thereof, through influence exerted by an electric field from the conductive layer, and a method of forming the same and, more particularly, it is advantageous in the case where the semiconductor region and the conductive layer are maintained at high potentials of substantially identical degrees and a high vol rage is applied between the conductive layer and the semiconductor substrate.
2. Description of the Background Art
A PWM inverter circuit is generally known as a circuit for driving a load such as a brushless motor. FIG. 1 is a schematic block diagram showing a single phase of such a PWM inverter. Power switching devices such as power MOS transistors 2 and 3 are totem-pole connected between a high-potential power line 1 and the ground. An output of this phase is derived from the junction between the power MOS transistors 2 and 3, and supplied to a load. Upper and lower arm driving circuits 4 and 5 receive upper and lower arm control signals from a control circuit (not shown), to convert the control signals into gate signals for turning on/off the power MOS transistors 2 and 3 of upper and lower arms, respectively, and supply the same to the power MOS transistors 2 and S.
FIG. 2 is a sectional view showing a state of insulation/isolation of the upper and lower arm driving circuits 4 and 5 formed on one chip 5. The upper arm driving circuit 4 is formed in a region 8 which is defined in an island 7, and the lower arm driving circuit 5 is formed in an island 9. Since the power MOS transistor 2 of the upper arm operates in a high-voltage region and, therefore, the upper arm driving circuit 4 for driving the power MOS transistor 2 must also operate in a high-voltage region, the potential of the region 8 provided with the upper arm driving circuit 4 is extremely increased. In order to sufficiently ensure breakdown voltage, therefore, the n.sup.- -type region 8 is defined in the island 7 by enclosing it an n.sup.+ -type buried diffusion region 10 and an n-type diffusion region 11, to form the upper arm driving circuit 4 in this region 8. The islands 7 and 9 are formed by separating an n.sup.- -type epitaxial layer which is formed on a p.sup.- -type semiconductor substrate 12 by a p-type isolating diffusion region 13. Since an output/input aluminium interconnection for the region 8 must pass above an end region 7a, the region 7a is necessary to be provided with a structure for moderating an electric field from the interconnection in order to prevent the decrease of breakdown voltage due to the existence of the interconnection.
FIG. 3 is a sectional view showing a portion around the end region 7a of the high-voltage island 7 in detail. An insulating film 14 is formed on the p.sup.- -type semiconductor substrate 12, and an aluminum interconnection 15 is formed on the insulating film 14. The aluminum interconnection is electrically connected with the n-type diffusion region 11, and extends toward the low-voltage island 9 above the high-voltage holding island 7 across the end region 7a of the island 7. Conductive plates 16a to 16e of polysilicon are provided in the insulating film 14 provided under the aluminum interconnection 15. The leftmost and rightmost conductive plates 16a and 16e are connected to the p-type isolating diffusion region 13 and the n-type diffusion region 11, respectively, while the intermediate conductive plates 16b to 16d are kept in electrically floating states. The conductive plates 16a to 16e are so arranged that adjacent pairs of end portions thereof overlap with each other.
The p.sup.- -type semiconductor substrate 12 and the p-type isolating diffusion region 13 are at low potentials, while the island 7, which is p-n junction-isolated from the same, is at a high potential. Therefore, depletion layers bidirectionally extend from the p-n junction interface, such that the n.sup.- -type region 7a, which has particularly low impurity concentration, is completely depleted. Dotted lines appearing in FIG. 3 represent equipotential lines of the depletion layers extending into the island 7 within those bidirectionally extending from the p-n junction interface.
The conductive plate 16a is fixed at the low potential of the p-type separation diffusion region 13, and the conductive plate 16e is fixed at the high potential of the n-type diffusion region 11. The floating conductive plates 16b, 16c and 16d are fixed at certain potentials by a first capacitance between the conductive plates 16a to 16e and a second capacitance between the aluminum wiring 15 and the respective conductive plates 16a to 16e. It is possible to fix the potentials of the conductive plates 16a to 16e to substantially linearly change from a low level to a high level by optimizing the first and second capacitances. Thus, it is possible to prevent concentration of electric fields caused in the end region 7a of the island 7, particularly on its surface, through influence exerted by an electric field from the high-potential aluminum interconnection 15. Consequently, the equipotential lines in the depletion layers are not concentrated toward the p-type isolating diffusion region 13 on the surface of the n.sup.- -type region 7a but are distributed with appropriate spreading, as shown by the dotted lines in FIG. 3. Thus, the island 7, which is provided with the upper arm driving circuit 4 operating in a high-voltage region, is increased in breakdown voltage.
In the aforementioned conventional structure for preventing field concentration in a semiconductor device, adjacent pairs of end portions of the conductive plates 16a to 16e must overlap with each other in order to prevent influence exerted by an electric field from the high-potential aluminum interconnection 15. If the end portions do not overlap with each other, the capacitance across the conductive plates 16a to 16e is so extremely reduced that the potential of the floating conductive plate 16b or 16c, which is close to the low-potential side, is excessively increased or the electric field from the high-potential aluminum interconnection 15 directly exerts influence on the n.sup.- -type region 7a. As a result, field concentration is caused on the surface of the n.sup.- -type region 7a, to reduce breakdown voltage of the island 7.
End portions of each adjacent pair of conductive plates must be provided in different vertical positions so that adjacent pairs of the end portions of the conductive plates 16a to 16e can overlap with each other. Therefore, it is necessary to carry out two steps of forming polysilicon layers for such conductive plates. This also applies to a case of employing aluminum as a material for the conductive plates 16a to 16e. The capacitance across the conductive plates 16a to 16e is varied due to influence exerted by mask misalignment caused in twice patterning of the polysilicon layers. Thus, the conventional structure for preventing field concentration in a semiconductor device is inferior in stability of characteristics (i.e., increased in dispersion) due to complicated steps, and the yield thereof is reduced.